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integrated silicon solution, inc. www.issi.com 1-800-379-4774 1 rev. c 02/16/2012 copyright ? 2012 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specifcation and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtain the lat- est version of this device specifcation before relying on any published information and before placing orders for products. integrated silicon solution, inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex- pected to cause failure of the life support system or to signifcantly affect its safety or effectiveness. products are not authorized for use in such applications unless integrated silicon solution, inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of integrated silicon solution, inc is adequately protected under the circumstances IS41C16100C is41lv16100c features ? ttl compatible inputs and outputs; tristate i/o ? refresh interval: ? auto refresh mode: 1,024 cycles /16 ms ? ras -only, cas -before-ras (cbr), and hidden self refresh mode: 1,024 cycles /128 ms ? jedec standard pinout ? single power supply: 5v 10% (IS41C16100C) 3.3v 10% (is41lv16100c) ? byte write and byte read operation via two cas ? industrial temperature range: -40 o c to +85 o c description the issi IS41C16100C and is41lv16100c are 1,048,576 x 16-bit high-performance cmos dynamic random ac- cess memories. these devices offer a cycle access called extended data out (edo) page mode. edo page mode allows 1,024 random accesses within a single row with access cycle time as short as 30 ns per 16-bit word. it is asynchronous, as it does not require a clock signal input to synchronize commands and i/o. these features make the is41c/41lv16100c ideally suited for high-bandwidth graphics, digital signal processing, high-performance computing systems, and peripheral applications that run without a clock to synchronize with the dram. the is41c/41lv16100c is packaged in a 42-pin 400-mil soj and 400-mil 50/44 pin tsop (type ii). 1mx16 16mb dram with edo page mode key timing parameters parameter -50 unit max. ras access time (t rac ) 50 ns max. cas access time (t cac ) 14 ns max. column address access time (t aa ) 25 ns min. edo page mode cycle time (t pc ) 30 ns min. read/write cycle time (t rc ) 85 ns february 2012
2 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. c 02/16/2012 IS41C16100C is41lv16100c pin configurations 50(44)-pin tsop (type ii) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 vdd i/o0 i/o1 i/o2 i/o3 vdd i/o4 i/o5 i/o6 i/o7 nc nc we ras nc nc a0 a1 a2 a3 vdd gnd i/o15 i/o14 i/o13 i/o12 gnd i/o11 i/o10 i/o9 i/o8 nc lcas ucas oe a9 a8 a7 a6 a5 a4 gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 vdd i/o0 i/o1 i/o2 i/o3 vdd i/o4 i/o5 i/o6 i/o7 nc nc nc we ras nc nc a0 a1 a2 a3 vdd gnd i/o15 i/o14 i/o13 i/o12 gnd i/o11 i/o10 i/o9 i/o8 nc nc lcas ucas oe a9 a8 a7 a6 a5 a4 gnd pin descriptions a0-a9 address inputs i/o0-15 data inputs/outputs 6c write enable oc output enable 102 row address strobe p/02 upper column address strobe y/02 lower column address strobe v // power gnd ground nc no connection 42-pin soj
integrated silicon solution, inc. www.issi.com 1-800-379-4774 3 rev. c 02/16/2012 IS41C16100C is41lv16100c functional block diagram o e we l cas ucas cas we oe data i/o bus column decoders sense amplifiers memory array 1,048,576 x 16 row decoder data i/o buffers cas clock generator we control logics oe control logic i/o0-i/o15 ras ras a0-a9 ras clock generator refresh counter address buffers
4 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. c 02/16/2012 IS41C16100C is41lv16100c truth table (5) function ? ras? lcas? ucas? we? oe address t r / t c i/o standby h x x x x x high-z read: word l l l h l row/col d out read: lower byte l l h h l row/col lower byte, d out upper byte, high-z read: upper byte l h l h l row/col lower byte, high-z upper byte, d out write: word (early write) l l l l x row/col d in write: lower byte (early write) l l h l x row/col lower byte, d in upper byte, high-z write: upper byte (early write) l h l l x row/col lower byte, high-z upper byte, d in read-write (1,2) l l l h l l h row/col d out , d in edo page-mode read (2) 1st cycle: l h l h l h l row/col d out 2nd cycle: l h l h l h l na/col d out any cycle: l l h l h h l na/na d out edo page-mode write (1) 1st cycle: l h l h l l x row/col d in 2nd cycle: l h l h l l x na/col d in edo page-mode (1,2) 1st cycle: l h l h l h l l h row/col d out , d in read-write 2nd cycle: l h l h l h l l h na/col d out , d in hidden refresh read (2) l h l l l h l row/col d out write (1,3) l h l l l l x row/col d out ras-only refresh l h h x x row/na high-z cbr refresh (4) h l l l h x x high-z notes: 1. these write cycles may also be byte write cycles (either lcas or ucas active). 2. these read cycles may also be byte read cycles (either lcas or ucas active). 3. early write only. 4. at least one of the two cas signals must be active (lcas or ucas). 5. commands valid only after proper initialization.
integrated silicon solution, inc. www.issi.com 1-800-379-4774 5 rev. c 02/16/2012 IS41C16100C is41lv16100c functional description the is41c/41lv16100c is a cmos dram optimized for high-speed bandwidth, low power applications. during read or write cycles, each bit is uniquely addressed through the 16 address bits. these are entered ten bits (a0-a9) at time. the row address is latched by the row address strobe (ras). the column address is latched by the column address strobe (cas). ras is used to latch the frst nine bits and cas is used to latch the latter nine bits. the is41c/41lv16100c has two cas controls, lcas and ucas. the lcas and ucas inputs internally generates a cas signal functioning in an identical manner to the single cas input on the other 1m x 16 drams. the key difference is that each cas controls its corresponding i/o tristate logic ( in conjunction with oe and we and ras). lcas controls i/ o0 through i/o7 and ucas controls i/o8 through i/o15. the is41c/41lv16100c cas function is determined by the frst cas (lcas or ucas) transitioning low and the last transitioning back high. the two cas controls give the IS41C16100C and is41lv16100c both byte read and byte write cycle capabilities. memory cycle a memory cycle is initiated by bring ras low and it is terminated by returning both ras and cas high. to ensures proper device operation and data integrity any memory cycle, once initiated, must not be ended or aborted before the minimum t ras time has expired. a new cycle must not be initiated until the minimum precharge time t rp , t cp has elapsed. read cycle a read cycle is initiated by the falling edge of cas or oe, whichever occurs last, while holding we high. the column address must be held for a minimum time specifed by t ar . data out becomes valid only when t rac , t aa , t cac and t oea are all satisfed. as a result, the access time is dependent on the timing relationships between these parameters. write cycle a write cycle is initiated by the falling edge of cas and we, whichever occurs last. the input data must be valid at or before the falling edge of cas or we , whichever occurs frst. auto refresh cycle to retain data, 1,024 refresh cycles are required in each 16 ms period. there are two ways to refresh the memory. 1. by clocking each of the 1,024 row addresses (a0 through a9) with ras at least once every t ref max. any read, write, read-modify-write or ras -only cycle refreshes the addressed row. 2. using a cas -before-ras refresh cycle. cas -before- ras refresh is activated by the falling edge of ras , while holding cas low. in cas -before-ras refresh cycle, an internal 9-bit counter provides the row addresses and the external address inputs are ignored. cas -before-ras is a refresh-only mode and no data access or device selection is allowed. thus, the output remains in the high-z state during the cycle. self refresh cycle the self refresh allows the user a dynamic refresh, data retention mode at the extended refresh period of 128 ms. i.e., 125 s per row when using distributed cbr refreshes. the feature also allows the user the choice of a fully static, low power data retention mode. the optional self refresh feature is initiated by performing a cbr refresh cycle and holding ras low for the specifed tras. the self refresh mode is terminated by driving ras high for a minimum time of trp. this delay allows for the completion of any internal refresh cycles that may be in process at the time of the ras low-to-high transition. if the dram controller uses a distributed refresh sequence, a burst refresh is not required upon exiting self refresh. however, if the dram controller utilizes a ras -only or burst refresh sequence, all 1,024 rows must be refreshed within the average internal refresh rate, prior to the resumption of normal operation. extended data out page mode edo page mode operation permits all 1,024 columns within a selected row to be randomly accessed at a high data rate. in edo page mode read cycle, the data-out is held to the next cas cycles falling edge, instead of the rising edge. for this reason, the valid data output time in edo page mode is extended compared with the fast page mode. in the fast page mode, the valid data output time becomes shorter as the cas cycle time becomes shorter. there- fore, in edo page mode, the timing margin in read cycle is larger than that of the fast page mode even if the cas cycle time becomes shorter. in edo page mode, due to the extended data function, the cas cycle time can be shorter than in the fast page mode if the timing margin is the same. the edo page mode allows both read and write operations during one ras cycle, but the performance is equivalent to that of the fast page mode in that case. power-on during power-on, ras, ucas, lcas, and we must all track with v dd (high) to avoid current surges, and allow initialization to continue. an initial pause of 200 s is required followed by a minimum of eight initial- ization cycles (any combination of cycles containing a ras signal).
6 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. c 02/16/2012 IS41C16100C is41lv16100c absolute maximum ratings (1) symbol parameters rating unit v t voltage on any pin relative to gnd 5v C1.0 to +7.0 v 3.3v C0.5 to +4.6 v dd supply voltage 5v C1.0 to +7.0 v 3.3v C0.5 to +4.6 i out output current 50 ma p d power dissipation 1 w t a industrial operation temperature -40 to +85 c t stg storage temperature C55 to +125 c note: 1. stress greater than those listed under absolute maximum ratings may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. recommended operating conditions (at t a = -40c to +85c for industrial grade. voltages are referenced to gnd.) symbol parameter test condition min. typ. max. unit v dd supply voltage 5v 4.5 5.0 5.5 v 3.3v 3.0 3.3 3.6 v ih input high voltage 5v 2.4 v dd + 1.0 v 3.3v 2.0 v dd + 0.3 v il input low voltage 5v C1.0 0.8 v 3.3v C0.3 0.8 i il input leakage current any input 0v v in v dd C5 5 a other inputs not under test = 0v i io output leakage current output is disabled (hi-z) C5 5 a 0v v out v dd v oh output high voltage level i oh = C5.0 ma 5v 2.4 v i oh = C2.0 ma 3.3v 2.4 v ol output low voltage level i ol = 4.2 ma 5v 0.4 v i ol = 2.0 ma 3.3v 0.4 capacitance (1,2) symbol parameter max. unit c in 1 input capacitance: a0-a9 5 pf c in 2 input capacitance: ras, ucas, lcas, we, oe 7 pf c io data input/output capacitance: i/o0-i/o15 7 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c, f = 1 mhz.
integrated silicon solution, inc. www.issi.com 1-800-379-4774 7 rev. c 02/16/2012 IS41C16100C is41lv16100c electrical characteristics (1) (recommended operating conditions unless otherwise noted.) symbol parameter test condition v dd min. max. unit i dd 1 standby current: ttl ras, lcas, ucas v ih 5v 2 ma 3.3v 2 ma i dd 2 standby current: cmos ras, lcas, ucas v dd C 0.2v 5v 1 ma 3.3v 1 ma i dd 3 operating current: ras, lcas,?ucas, 5v 90 ma random read/write (2,3,4) address cycling, t rc = t rc (min.) 3.3v 90 average power supply current i dd 4 operating current: ras = v il , lcas, ucas, 5v 30 ma edo page mode (2,3,4) cycling t pc = t pc (min.) 3.3v 30 average power supply current i dd 5 refresh current: ras cycling, lcas, ucas v ih 5v 60 ma ras-only (2,3) t rc = t rc (min.) 3.3v 60 average power supply current i dd 6 refresh current: ras, lcas, ucas cycling 5v 60 ma cbr (2,3,5) t rc = t rc (min.) 3.3v 60 average power supply current notes: 1. an initial pause of 200 s is required after power-up followed by eight ras refresh cycles (ras-only or cbr) before proper device operation is assured. the eight ras cycles wake-up should be repeated any time the t ref refresh requirement is exceeded. 2. dependent on cycle rates. 3. specifed values are obtained with minimum cycle time and the output open. 4. column-address is changed once each edo page cycle. 5. enables on-chip refresh and address counters.
8 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. c 02/16/2012 IS41C16100C is41lv16100c ac characteristics (1,2,3,4,5,6) (recommended operating conditions unless otherwise noted.) -50 -60 symbol parameter min. max. min. max. units t rc random read or write cycle time 85 110 ns t rac access time from ras (6, 7) 50 60 ns t cac access time from cas (6, 8, 15) 14 15 ns t aa access time from column-address (6) 25 30 ns t ras ras pulse width 50 10k 60 10k ns t rp ras precharge time 30 40 ns t cas cas pulse width (26) 8 10k 10 10k ns t cp cas precharge time (9, 25) 9 10 ns t csh cas hold time (21) 50 60 ns t rcd ras to cas delay time (10, 20) 12 37 20 45 ns t asr row-address setup time 0 0 ns t rah row-address hold time 8 10 ns t asc column-address setup time (20) 0 0 ns t cah column-address hold time (20) 8 10 ns t ar column-address hold time 30 40 ns (referenced to ras) t rad ras to column-address delay time (11) 14 25 15 30 ns t ral column-address to ras lead time 25 30 ns t rpc ras to cas precharge time 5 5 ns t rsh ras hold time (27) 14 15 ns t rhcp ras hold time from cas precharge 37 37 ns t clz cas to output in low-z (15, 29) 0 0 ns t crp cas to ras precharge time (21) 5 5 ns t od output disable time (19, 28, 29) 3 12 3 12 ns t oe / t oea output enable time (15, 16) 14 15 ns t oehc oe high hold time from cas high 15 15 ns t oep oe high pulse width 10 10 ns t oes oe low to cas high setup time 5 5 ns t rcs read command setup time (17, 20) 0 0 ns t rrh read command hold time 0 0 ns (referenced to ras) (12) t rch read command hold time 0 0 ns (referenced to cas) (12, 17, 21) t wch write command hold time (17, 27) 8 10 ns t wcr write command hold time 40 50 ns (referenced to ras) (17)
integrated silicon solution, inc. www.issi.com 1-800-379-4774 9 rev. c 02/16/2012 IS41C16100C is41lv16100c ac characteristics (continued) (1,2,3,4,5,6) (recommended operating conditions unless otherwise noted.) -50 -60 symbol parameter min. max. min. max. units t wp write command pulse width (17) 8 10 ns t wpz we pulse widths to disable outputs 10 10 ns t rwl write command to ras lead time (17) 13 15 ns t cwl write command to cas lead time (17, 21) 8 15 ns t wcs write command setup time (14, 17, 20) 0 0 ns t dhr data-in hold time (referenced to ras) 39 40 ns t ach column-address setup time to cas precharge 15 15 ns during write cycle t oeh oe hold time from we during 14 15 ns read-modify-write cycle (18) t ds data-in setup time (15, 22) 0 0 ns t dh data-in hold time (15, 22) 8 15 ns t rwc read-modify-write cycle time 110 155 ns t rwd ras to we delay time during 65 85 ns read-modify-write cycle (14) t cwd cas to we delay time (14, 20) 26 40 ns t awd column-address to we delay time (14) 40 55 ns t pc edo page mode read or write 30 40 ns cycle time (24) t rasp ras pulse width in edo page mode 50 100k 60 100k ns t cpa access time from cas precharge (15) 30 35 ns t prwc edo page mode read-write 56 56 ns cycle time (24) t coh data output hold after cas low 5 5 ns t off output buffer turn-off delay from 3 12 3 15 ns ? ? cas or ras (13,15,19, 29) t whz output disable delay from we 3 10 3 15 ns t clch last cas going low to first cas 10 10 ns returning high (23) t csr cas setup time (cbr refresh) (30, 20) 5 5 ns t chr cas hold time (cbr refresh) (30, 21) 8 10 ns t ord oe setup time prior to ras during 0 0 ns hidden refresh cycle t wrp we setup time (cbr refresh) 5 5 ns t wrh we hold time (cbr refresh) 8 10 ns t ref auto refresh period (1,024 cycles) 16 16 ms t ref self refresh period (1,024 cycles) 128 128 ms t t transition time (rise or fall) (2, 3) 1 50 1 50 ns note: the -60 timing parameters are shown for reference only. the -50 speed option supports 50ns and 60ns timing specifcations.
10 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. c 02/16/2012 IS41C16100C is41lv16100c notes: 1. an initial pause of 200 s is required after power-up followed by eight ras refresh cycle (ras-only or cbr) before proper device operation is assured. the eight ras cycles wake-up should be repeated any time the t ref refresh requirement is exceeded. 2. v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times, are measured between v ih and v il (or between v il and v ih ) and assume to be 1 ns for all inputs. 3. in addition to meeting the transition rate specifcation, all input signals must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 4. if cas and ras = v ih , data output is high-z. 5. if cas = v il , data output may contain data from the last valid read cycle. 6. measured with a load equivalent to one ttl gate and 50 pf. 7. assumes that t rcd t rcd (max). if t rcd is greater than the maximum recommended value shown in this table, t rac will increase by the amount that t rcd exceeds the value shown. 8. assumes that t rcd t rcd (max). 9. if cas is low at the falling edge of ras, data out will be maintained from the previous cycle. to initiate a new cycle and clear the data output buffer, cas and ras must be pulsed for t cp . 10. operation with the t rcd (max) limit ensures that t rac (max) can be met. t rcd (max) is specifed as a reference point only; if t rcd is greater than the specifed t rcd (max) limit, access time is controlled exclusively by t cac . 11. operation within the t rad (max) limit ensures that t rcd (max) can be met. t rad (max) is specifed as a reference point only; if t rad is greater than the specifed t rad (max) limit, access time is controlled exclusively by t aa . 12. either t rch or t rrh must be satisfed for a read cycle. 13. t off (max) defnes the time at which the output achieves the open circuit condition; it is not a reference to v oh or v ol . 14. t wcs , t rwd , t awd and t cwd are restrictive operating parameters in late write and read-modify-write cycle only. if t wcs t wcs (min), the cycle is an early write cycle and the data output will remain open circuit throughout the entire cycle. if t rwd t rwd (min), t awd t awd (min) and t cwd t cwd (min), the cycle is a read-write cycle and the data output will contain data read from the selected cell. if neither of the above conditions is met, the state of i/o (at access time and until cas and ras or oe go back to v ih ) is indeterminate. oe held high and we taken low after cas goes low result in a late write (oe-controlled) cycle. 15. output parameter (i/o) is referenced to corresponding cas input, i/o0-i/o7 by lcas and i/o8-i/o15 by ucas. 16. during a read cycle, if oe is low then taken high before cas goes high, i/o goes open. if oe is tied permanently low, a late write or read-modify-write is not possible. 17. write command is defned as we going low. 18. late write and read-modify-write cycles must have both t od and t oeh met (oe high during write cycle) in order to ensure that the output buffers will be open during the write cycle. the i/os will provide the previously written data if cas remains low and oe is taken back to low after t oeh is met. 19. the i/os are in open during read cycles once t od or t off occur. 20. the frst cas edge to transition low. 21. the last cas edge to transition high. 22. these parameters are referenced to cas leading edge in early write cycles and we leading edge in late write or read- modify-write cycles. 23. last falling cas edge to frst rising cas edge. 24. last rising cas edge to next cycles last rising cas edge. 25. last rising cas edge to frst falling cas edge. 26. each cas must meet minimum pulse width. 27. last cas to go low. 28. i/os controlled, regardless ucas and lcas. 29. the 3 ns minimum is a parameter guaranteed by design. 30. enables on-chip refresh and address counters. ac test conditions output load: two ttl loads and 100 pf (v dd = 5.0v 10%) one ttl load and 50 pf (v dd = 3.3v 10%) input timing reference levels: v ih = 2.4v, v il = 0.8v (v dd = 5.0v 10%); v ih = 2.0v, v il = 0.8v (v dd = 3.3v 10%) output timing reference levels: v oh = 2.4v, v ol = 0.4v (v dd = 5v 10%, 3.3v 10%)
integrated silicon solution, inc. www.issi.com 1-800-379-4774 11 rev. c 02/16/2012 IS41C16100C is41lv16100c read cycle note: 1. t off is referenced from rising edge of ras or cas, whichever occurs last. t ras t rc t rp t ar t cah t asc t rad t ral oe i/o we address ucas/lcas ras row column row open open valid data t csh t cas t rsh t crp t clch t rcd t rah t asr t rrh t rch t rcs t aa t cac t off (1) t rac t clc t oes t oe t od dont care undefned
12 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. c 02/16/2012 IS41C16100C is41lv16100c early write cycle (oe = don't care) t ras t rc t rp t ar t cah t asc t rad t ral t ach i/o we address ucas/lcas ras row column row t csh t cas t rsh t crp t clch t rcd t rah t asr t cwl t wcr t wch t rwl t wp t wcs t dh t ds t dhr valid data dont care
integrated silicon solution, inc. www.issi.com 1-800-379-4774 13 rev. c 02/16/2012 IS41C16100C is41lv16100c read write cycle (late write and read-modify-write cycles) t ras t rwc t rp t ar t cah t asc t rad t ral t ach we oe address ucas/lcas ras row column row t csh t cas t rsh t crp t clch t rcd t rah t asr t rwd t cwl t cwd t rwl t awd t wp t rcs t cac t clz t ds t dh t oeh t od t oe t rac t aa i/o open open valid d out valid d in dont care undefned
14 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. c 02/16/2012 IS41C16100C is41lv16100c edo-page-mode read cycle note: 1. t pc can be measured from falling edge of cas to falling edge of cas, or from rising edge of cas to rising edge of cas. both measurements must meet the t pc specifcations. t rasp t rp address ucas/lcas ras row row t cas, t clch t crp t rcd t csh t cp t cas, t clch t cah t cas, t clch t ral t rsh t cp t cp t pc (1) t asr t rah t rad t ar column column t cah t cah column t asc t asc oe i/o we open ope n valid data t aa t aa t cpa t cac t cac t rac t coh t clz t oep t oe t oes t oes t od t oe t oehc valid data t rch t rrh t aa t cpa t cac t off t clz valid data t od t asc t rcs dont care undefned
integrated silicon solution, inc. www.issi.com 1-800-379-4774 15 rev. c 02/16/2012 IS41C16100C is41lv16100c edo-page-mode early-write cycle t rasp t rp address ucas/lcas ras row row t cas, t clch t crp t rcd t csh t cp t cas, t clch t cah t cas, t clch t ral t rsh t cp t cp t pc t asr t rah t rad t ar t ach column column t ach t ach t cah t cah column t asc t asc oe i/o we valid data t asc t wcs t wch t cwl t wp t rhcp t wcs t wch t cwl t wp t ds t dh t dhr t wcr t wcs t wch t cwl t wp valid data t ds t dh valid data t ds t rwl t dh dont care
16 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. c 02/16/2012 IS41C16100C is41lv16100c edo-page-mode read-write cycle (late write and read-modify write cycles) note: 1. t pc can be measured from falling edge of cas to falling edge of cas, or from rising edge of cas to rising edge of cas. both measurements must meet the t pc specifcations. dont care undefned t rasp t rp address ucas/lcas ras row row t crp t rcd t csh t cp t cah t cas, t clch t ral t rsh t cp t cp t rah t rad t ar t asr column column t cah t cah column t asc t asc t cas, t clch t cas, t clch oe i/o we t asc t rwd t rcs t cwl t wp t awd t cwd t dh t ds t cac t clz t awd t cwd t cwl t wp t awd t cwd t cwl t rwl t wp open open d in d out t oe t oe t oe t od t oeh t od t od t dh t ds t cpa t aa t cac t clz d in d out t dh t ds t cac t clz d in d out t cpa t aa t rac t aa t pc / t prwc (1)
integrated silicon solution, inc. www.issi.com 1-800-379-4774 17 rev. c 02/16/2012 IS41C16100C is41lv16100c edo-page-mode read-early-write cycle (pseudo read-modify write) t rasp t rp address ucas/lcas ras row row t crp t rcd t pc t csh t cp t cah t cas t ral t rsh t cp t cp t ach t rah t rad t ar t asr column (a) column (n) t cah t cah column (b) t asc t asc t cas t cas oe i/o we t asc t cac t rch t dh open open valid data (a ) t oe t wcs t cac t coh d in t cpa t wch t rac t aa t pc valid data (b ) t whz t ds t rcs t aa dont care
18 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. c 02/16/2012 IS41C16100C is41lv16100c ac waveforms read cycle (with we-controlled disable) ras -only refresh cycle (oe, we = don't care) t ar t cah t asc t asc t rad oe i/o we address ucas/lcas ras row column open open valid data t csh t cas t crp t rcd t cp t rah t asr t rch t rcs t wpz t rcs t aa t cac t whz t rac t clz t clz t oe t od column t ras t rc t rp i/o address ucas/lcas ras row row open t crp t rah t asr t rpc dont care undefned dont care
integrated silicon solution, inc. www.issi.com 1-800-379-4774 19 rev. c 02/16/2012 IS41C16100C is41lv16100c hidden refresh cycle (1) (we = high; oe = low) cbr refresh cycle (addresses; oe = don't care) notes: 1. a hidden refresh may also be performed after a write cycle. in this case, we = low and oe = high. 2. t off is referenced from rising edge of ras or cas, whichever occurs last. t ras t ras t rp t rp i/o ucas/lcas ras we open t cp t rpc t csr t chr t rpc t csr t chr t wrp t wrp t wrh t wrh t ras t ras t rp ucas/lcas ras t crp t rcd t rsh t chr t ar t asc t rad address row column t rah t asr t ral t cah i/o open open valid data t aa t cac t rac t clz t off (2) oe t oe t ord t od dont care undefned
20 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. c 02/16/2012 IS41C16100C is41lv16100c ordering information : 3.3v industrial range: -40 c to +85c speed (ns) order part no. package 50 is41lv16100c-50ki 400-mil soj is41lv16100c-50kli 400-mil soj, lead-free is41lv16100c-50ti 400-mil tsop (type ii) is41lv16100c-50tli 400-mil tsop (type ii), lead-free ordering information : 5v industrial range: -40 c to +85c speed (ns) order part no. package 50 IS41C16100C-50ki 400-mil soj IS41C16100C-50kli 400-mil soj, lead-free IS41C16100C-50ti 400-mil tsop (type ii) IS41C16100C-50tli 400-mil tsop (type ii), lead-free note: the -50 speed option supports 50ns and 60ns timing specifcations.
integrated silicon solution, inc. www.issi.com 1-800-379-4774 21 rev. c 02/16/2012 IS41C16100C is41lv16100c
22 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. c 02/16/2012 IS41C16100C is41lv16100c

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